1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device and a manufacturing method thereof in which material of high dielectric constant is used for a capacitor dielectric film of a DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
DRAM has been known as a semiconductor memory device which allows random input and output of memory information. The DRAM generally has a memory cell array portion which is a memory area with a large amount of memory information stored therein, and a peripheral circuit portion which is necessary for the external input and Output.
A plurality of memory cells each for storing unit memory information are arranged on a matrix in the memory cell array portion which occupies a large area on a semiconductor chip. One memory cell generally consists of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected to the MOS transistor. Such a memory cell is referred to as a one-transistor/one-capacitor type memory cell.
The integration of a memory cell array can be improved easily in this one-transistor/one-capacitor type memory cell because of its simple structure. Such a memory cell is therefore widely utilized in a DRAM of large capacity.
Memory cells of conventional DRAMs can be classified into several types according to their capacitor structures. One of them is referred to as a stacked type capacitor. The stacked type capacitor is structured such that the main portion in the capacitor structure is extended over a gate electrode of MOS transistor and a field oxide film, thereby increasing the opposing areas between capacitor electrodes.
Owing to such a characteristic of the stacked type capacitor, certain capacitance of a capacitor could be secured even if circuit elements are miniaturized as a semiconductor memory device is highly integrated. The stacked type capacitor is thus widely utilized as the integration of a semiconductor memory device is promoted.
However, when the elements are further miniaturized, securing the certain capacitance of a capacitor is difficult in, for example, a DRAM of 256 Mbit, even if the stacked type capacitor is used.
In an attempt of increasing the capacitance of a capacitor, a capacitor dielectric film formed of material having high dielectric constant (e.g. Barium Strontium Titanate (BST)) is used.
With reference to FIG. 19, a description will be given as to a cross sectional structure of a memory cell of a DRAM in which material having high dielectric constant is used for a capacitor dielectric film.
A source region 6 and drain regions 7a, 7b formed of impurity diffusion regions are provided at a major surface of a semiconductor substrate 1. On the major surface of semiconductor substrate 1, a gate electrode 4a is formed with a gate oxide film 5a therebetween, and a gate electrode 4b is further formed with a gate oxide film 5b therebetween. A field oxide film 2 is provided at a prescribed region of the major surface of semiconductor substrate 1 for defining an active region.
In source region 6, a buried bit line 9 is provided for gate electrodes 4a and 4b with gate protection oxide films 8a and 8b interposed, and is covered with an oxide film 10.
An MOS transistor 3a is constituted by gate electrode 4a, source region 6 and drain region 7a, and an MOS transistor 3b is constituted by gate electrode 4b, source region 6 and drain region 7b.
A polysilicon plug 12 is provided within a contact hole 11a formed in an interlayer insulating film 11, and electrically connected to drain region 7b.
Barrier metal layers 13a, 13b are formed on polysilicon plug 12 to cover interlayer insulating film 11, and capacitor lower electrodes 14a, 14b are formed on barrier metal layers 13a, 13b.
A dielectric film 15 of material having high dielectric constant is further provided on capacitor lower electrodes 14a and 14b to cover barrier metal layers 13a, 13b and the surface of interlayer insulating film 11. An upper electrode 16 is further provided to cover high dielectric constant material 15. It is noted that platinum is used for lower electrode 14b and upper electrode 16.
On upper electrode 16, first aluminum interconnections 18a, 18b, 18c are formed with an interlayer insulating film 17 therebetween, and a first aluminum interlayer insulating film 19 is provided to cover first aluminum interconnections 18a, 18b, 18c. A second aluminum interconnection 20 is provided on first aluminum interlayer insulating film 19.
An operation of a memory cell in a DRAM structured as above will be next described.
The stacked type capacitor shown in FIG. 19 is utilized as a cell capacitor or the like in a semiconductor integrated circuit. In this case, information is stored by accumulating charges of signals controlled by MOS transistor 3b, for example, in capacitor lower electrode 14b formed on the same substrate as MOS transistor 3b.
The amount Q of accumulated charges can be expressed as follows using a relative dielectric constant .di-elect cons. between a capacitor region S and dielectric film 15 and a film thickness t of dielectric film 15. EQU Q=.di-elect cons..sub.o .multidot..di-elect cons..multidot.S.multidot.V/t
where .di-elect cons..sub.o denotes a dielectric constant under vacuum and V denotes voltage applied to a capacitor.
The amount Q of charges should be sufficiently large but should not cause a memory error called a soft error due to excess charges generated by ionizing radiation.
In a semiconductor circuit of lower integration, a silicon oxide film formed by thermally oxidizing silicon, or a silicon nitride film formed by CVD method has been conventionally used as a dielectric film. However, as circuit elements are highly integrated and capacitor region S is decreased, to obtain charge accumulation large enough but will not cause a soft error becomes impossible with above described silicon oxide film or silicon nitride film.
As shown in FIG. 19, the high dielectric constant material having high relative dielectric constant, such as barium strontium titanate, tantalum oxide, lead titanate, or strontium titanate is utilized as a dielectric film.
For example, the high relative dielectric constant of lead titanate is 1000 or more, and that of strontium titanate is approximately 200. An enhanced insulating property could be obtained when a film of above material is formed avoiding oxide defects. Other than the lead titanate, barium titanate is known as material for a dielectric film.
A thin film of, e.g., strontium titanate is usually formed using the reactive sputtering or CVD method. In this case, a film is often formed in an oxidation ambient at a high temperature of approximately 500-700.degree. C. in order to prevent an increase of leak current due to the oxide defect.
As described above, platinum having high resistance to oxidation is utilized as material for lower electrode in a thin film capacitor in which the lead titanate is used. Barrier metal layers 13a, 13b are further necessary between lower electrode 14b and polysilicon plug 12 as barrier metal (diffusion preventing films) having the conductivity which prevents diffusion of silicon and oxygen, in order to prevent oxidation of that portion of a silicon substrate which is electrically connected to the lower electrode.
However, in the capacitor structure in the conventional DRAM shown in FIG. 19, there is a step portion of height h.sub.1 on the top of contact hole 11a.
The step portion is generated in the steps of forming a polysilicon film according to CVD and etching back the polysilicon film in order to form a polysilicon plug 12 within contact hole 11a.
Although the height of the step portion could be reduced by adjusting etching conditions, it is impossible to eliminate the step portion because the polysilicon film has a higher etching rate than interlayer insulating film 11.
Accordingly, there are step portions also on the surfaces of barrier metal layer 13b, lower electrode 14b and dielectric film 15 according to the step portion in contact hole 11a.
An almost right-angled portion is accordingly formed in lower electrode 14b in the step portion as enclosed by X in FIG. 19. Electric field is concentrated in the right-angled portion upon an application of voltage, producing a high electric current. As a result, a degradation of dielectric film 15 contacting with the upper surface of the right-angled portion is accelerated, resulting in a shorter lifetime and a lower reliability of the capacitor.